Multiplier is one of the most common basic operations for digital signal processing. When performing a digital signal processing, in order to prevent data's bit width from overflow as the operation burden increases, therefore multiplication operation usually incorporates a reduced (or fixed) width characteristic so as to prevent the occurrence of the case of the numerical overflow during the process of the operation. Generally speaking, the reduced-width characteristic is commonly realized by employing a post-truncated multiplier, where the truncation operation is executed at the output of the multiplier in order to maintain the fixed width of bits. In contrast to the post-truncated multiplier, the direct-truncated multiplier only executes a partial product accumulation on the portions that are willing to preserve the output bit of the multiplication so as to reduce the computation complexity; but, however, usually it will result in a relatively large error.
For the direct-truncated fixed-width multiplier, the bit width of input/output is the same; and for the fixed-width multiplier, the error is compensated by adding a number. However, error compensation methods proposed in prior arts are only applicable for multipliers that utilize a single partial product generating approach, and most of them need to be accompanied with an acquisition of a large amount of simulation auxiliary compensated terms. Because of the lack of effective analysis method, it is difficult to further apply to the system-level analysis. Therefore, a direct-truncated multiplier of the known art only realizes the partial product accumulation corresponding to the remaining parts after truncation.
Figure depicts a circuit block diagram of a well-known multiplier, in which the bit width of an input data A is n1, and the bit width of an input data B is n2. The product of these two inputs has a bid width of (n1+n2) bits. This product must be truncated by the truncator (denoted by T) in order to keep the bit width at n (n£n1+n2) bits and therefore to prevent overflow.
Although there are many kinds of method being proposed in the literature to compensate for this error, however, they all are applicable for those multipliers which utilize a certain partial product generating method. Hereafter a survey of patent literature and non-patent literature relevant to the present invention will be given and analyzed as follows:    1. R.O.C. Patent No. 396321, Jul. 1, 2000, “Low-Error Fixed-Width 2's Complement Parallel Multiplier.” This patent application only provided a compensation for a 2's complement fix-width multiplier, which may dynamically generate a quantity of compensation in accordance with the input value of the multiplier, but, however, due to the lack of theoretic analysis, it is not able to mitigate errors in accordance with the statistical characteristics of the input data, and furthermore it is not applicable for the multipliers that adopt different partial products generating methods.    2. R.O.C. Patent No. 484092, Apr. 21, 2002, “A Reducible Bit Length Low-Error Multiplier.” This patent application provided a dynamic compensation method for a 2's complement and modified Booth multipliers. The mechanism for generating an amount of compensation is simple, but is not able to efficiently compensate for errors.    3. K. K. Parhi, J. G. Chung, K. C. Lee, and K. J. Cho, “Low-Error Fixed-Width Modified Booth Multiplier,” Dec. 20, 2005, U.S. Pat. No. 6,978,426B2. This patent application provided a dynamic compensation method for the modified Booth multiplier, which is able to effectively compensate for errors; but, however, the hardware complexity for generating a quantity of compensation may increase as the width of the input of the multiplier become larger.    4. Y. C. Lim, “Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications,” IEEE Trans. Computers, Vol. 41, pp. 1333-1336, October 1992. This non-patent literature proposed generating a constant of compensation via a preliminary analysis, and also pointed out the concept of dynamic compensation, but, however, is lack of a detailed and concrete analysis and realization method.    5. M. J. Schulte and E. S. Jr., “Truncated Multiplication with Correction Constant,” in Workshop on VLSI Signal Processing, October 1993, pp. 388-396.    6. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-Efficient Multipliers for Digital Signal Processing Applications,” IEEE Trans. Circuits Syst. II, Vol. 43, pp. 90-95, February 1996.            (A) The non-patent literature, item 5 and item 6 mentioned above, both proposed a constant compensation method, which is not able to effectively compensate for errors.        (B) The non-patent literature, item 4 to item 6 mentioned above, put a special emphasis on the constant compensation method, which, besides being not able to effectively compensate for errors, it is also difficult to change the way of analysis in accordance with different generating method for partial products.            7. T. B. Juang and S. F. Hsiao, “Low-Error Carry-Free Fixed-Width Multipliers with Low-Cost Compensation Circuits,” IEEE Trans. Circuits Syst. II, Vol. 52, No. 6, pp. 299-303, June 2005. This non-patent literature provided a dynamic compensation mechanism only for signed-magnitude modified Booth multiplier, and did not provide any other multiplication compensation method for different partial products generating methods.    8. L. D. Van and C. C. Yang, “Generalized Low-Error Area-Efficient Fixed-Width Multipliers,” IEEE Trans. Circuits Syst. I, Vol. 52, No. 8, pp. 1608-1619, August 2005. This non-patent literature can be treated as a derivative of the above-mentioned patent literature item 1, but these two methods were designed only for 2's complement fixed-width multipliers, and are not appropriate for other multipliers employing different partial products generating method.